Exemplary embodiments of the present invention relate to semiconductor designing technology, and more particularly, to a delay locked loop circuit.
A synchronous semiconductor memory device such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) transfers/receives data to/from an external device by using an internal clock synchronized with an external clock inputted from the external device such as a memory controller. It is important to temporally synchronize a data outputted from a memory with an external clock supplied from a memory controller to the memory to stably transfer data between the memory and the memory controller.
The data is outputted from the memory in synchronization with an internal clock. When the internal clock is supplied to the memory at first, it is supplied in synchronization with an external clock. The internal clock, however, becomes delayed as it goes through the constituent elements of the memory and when it is outputted from the memory, it is not synchronized with an external clock.
Therefore, in order to stably transfer the data outputted from the memory, the internal clock should be compensated by an offset corresponding to the time taken when the data is loaded on a bus so that the internal clock delayed as it goes through the constituent elements of the memory which transfers the data is positioned exactly at an edge or the center of an external clock supplied by the memory controller and thus the internal clock is synchronized with the external clock.
Among the clock synchronization circuits performing this operation are a Phase Locked Loop (PLL) circuit and a Delay Locked Loop (DLL) circuit.
When the external clock frequency differs from the internal clock frequency, a phase locked loop circuit is usually used because a frequency multiplication function is needed. However, when external clock frequency is the same as internal clock frequency, a delay locked loop circuit is usually used because the delay locked loop circuit is less affected by noise than the phase locked loop circuit and the delay locked loop circuit can be realized in a relatively small area.
In short, since semiconductor memory devices use the same frequency, they usually employ a delay locked loop circuit as a clock synchronization circuit.
Among the kinds of the delay locked loop circuit, a register-controlled delay locked loop circuit is widely used in a semiconductor memory device. The register-controlled delay locked loop circuit is equipped with a register that can store a fixed delay value and when a power source is cut off, the register-controlled delay locked loop circuit stores the fixed delay value in the register and when the power source is turned on, it loads the fixed delay value out of the register and uses it to fix the internal clock. In this way, it is possible to perform a clock synchronization operation at a time point when the phase difference between an internal clock and an external clock is relatively small during the initial operation of the semiconductor memory device. Also, the register-controlled delay locked loop circuit can reduce the time taken for synchronizing an internal clock with an external clock by controlling the varying width of the delay value stored in the register according to the phase difference between the internal clock and the external clock even after the initial operation.
FIG. 1 is a block diagram illustrating a conventional register-controlled delay locked loop circuit. Referring to FIG. 1, the conventional register-controlled delay locked loop circuit includes a phase comparison unit 100, a clock delay unit 120, and a delay duplication modeling unit 140. The phase comparison unit 100 compares the phase of a reference clock with the phase of a feedback clock FBCLK and generates a delay locked control signal DELAY_LOCK_CTRL corresponding to the comparison result. The clock delay unit 120 delays the reference clock REFCLK in response to the delay locked control signal DELAY_LOCK_CTRL for delay locking and outputs a delay locked clock DLLCLK. The delay duplication modeling unit 140 changes the delay locked clock DLLCLK to reflect the delay time of an actual output path of the reference clock REFCLK and outputs a feedback clock FBCLK.
Hereafter, a basic locking operation of the conventional register-controlled delay locked loop circuit having the above-described structure will be described. The phase of a reference clock REFCLK is delayed and outputted as a delay locked clock DLLCLK so as to synchronize a reference edge of the reference clock REFCLK with a reference edge of a feedback clock FBCLK. Herein, the reference edge of the reference clock REFCLK generally indicates a rising edge but there is no problem even if a falling edge becomes the reference edge. Since the delay locked clock DLLCLK reflects the actual delay condition of the reference clock REFCLK path and outputted as a feedback clock FBCLK, the phase difference between the reference clock REFCLK and the feedback clock FBCLK gradually decreases as the phase delay amount of the reference clock REFCLK increases.
However, the conventional register-controlled delay locked loop circuit should delay the phase of the reference clock REFCLK step by step for delay locking when it performs the operation of delaying the phase of the reference clock REFCLK and outputs a delay locked clock DLLCLK. To this end, although not directly illustrated in FIG. 1, the conventional register-controlled delay locked loop circuit delays the phase of the reference clock REFCLK step by step by using a plurality of delay cells each having a predetermined delay amount.
Since each delay cell is formed of an active device such as a NAND gate or an inverter, each delay cell may have a problem of a delay amount varying according to a change in the level of an external power source voltage VDD.